1. Technical Field
The present invention relates generally to a semiconductor circuit, and more particularly, to a phase detection circuit and a synchronization circuit using the same.
2. Related Art
A conventional synchronization circuit such as a phase locked loop (PLL) or delayed locked loop (DLL) determines whether a phase or delay time has been adjusted to a value within a desired range, or whether a delay lock or phase lock has been achieved, during a phase or delay time adjustment process.
The synchronization circuit may use a phase detection circuit to determine whether a delay lock or phase lock has been achieved.
The phase detection circuit compares a reference signal REFCLK to a comparison target signal FBCLK and generates a result signal PDOUT.
FIG. 1 is a waveform diagram to demonstrate a phase detection operation for the conventional synchronization circuit.
Referring to FIG. 1, when noise components such as jitter are contained in the reference signal REFCLK and the comparison target signal FBCLK, the phase detection circuit may output the result signal as an abnormal value.
When the phase detection circuit outputs the result signal PDOUT as an abnormal value, an operation error of the synchronization circuit may occur.